View CXA2542Q_1924337.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

description the CXA2542Q is a bipolar ic developed for cd player rf signal processing and servo control. features automatic focus bias adjustment circuit automatic tracking balance and gain adjustment circuits rf level control circuit interruption countermeasure circuit anti-shock circuit defect detection and prevention circuits rf 1-v amplifier, rf amplifier apc circuit focus and tracking error amplifier focus, tracking and sled servo control circuits focus ok circuit mirror detection circuit single power supply and dual power supplies applications cd players structure bipolar silicon monolithic ic absolute maximum ratings (ta = 25?) supply voltage v cc 12 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? allowable power dissipation p d 1400 mw recommended operating conditions operating supply voltage v cc ?v ee 3.0 to 5.5 v ?1 CXA2542Q e96y03-ps rf signal processing servo amplifier for cd player sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 48 pin qfp (plastic)
? 2 CXA2542Q block diagram p s 1 - 4 t m 1 - 7 t g 1 - 2 f s 1 - 4 i f b 1 - 6 b a l 1 - 4 t o g 1 - 4 d f c t o f e a m p f o . b i a s w i n d o w c o m p . t g f l t r k . g a i n w i n d o w c o m p . f i v a m p e i v a m p v e e v c c t g 1 t m 1 d f c t t r a c k i n g p h a s e c o m p e n s a t i o n i i l d a t a r e g i s t e r i n p u t s h i f t r e g i s t e r a d d r e s s d e c o d e r s e n s s e l e c t o r o u t p u t d e c o d e r v e e v e e e - f b a l a n c e w i n d o w c o m p . e f f e i f d f c t f l b f e _ o f e _ m t a _ m t g 2 t g u s r c h f g d f s e t l d r f t c r f _ m r f _ o r f _ i c b c c 1 f o k c c 2 c p p d 1 p d s l _ p s l _ o i s e t v c c c l k d a t a x r s t s l _ m c . o u t x l t s e n s 1 p d 2 i v a m p p d 1 i v a m p v c c v e e a p c v e e l a s e r p o w e r c o n t r o l r f s u m m i n g a m p v c c v e e l e v e l s f z c t z c a t s c b a l l b a l h t g l t g h f o l f o h l d o n l p c l l p c t g f l v e e v c c m i r r d f c t 1 v e e v c c d f c t c c 1 i s e t v c c v e e v c c t m 5 t m 6 v e e v c c t m 3 t m 4 f s e t t g 2 f o c u s p h a s e c o m p e n s a t i o n t m 7 v e e v c c f s 1 f s 2 d f c t f s 4 4 2 4 4 4 5 4 6 4 8 2 3 4 6 7 8 9 1 0 1 1 1 2 1 1 3 2 7 2 8 2 9 3 0 3 9 3 8 3 6 3 5 3 4 3 1 3 2 3 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 t m 2 v c c f z c c o m p . t z c c o m p . a t s c w i n d o w c o m p . m i r r f o k b a l 1 b a l 2 b a l 3 b a l 4 i f b 1 v e e v c c i f b 6 i f b 5 i f b 4 i f b 3 i f b 2 t o g 1 t o g 2 t o g 3 t o g 4 3 7 5 t a _ o s e n s 2 a t s c l p f i t e o v c t d f c t t z c f e o f z c p d 2 4 7 4 0 4 1 4 3 i i l t t l i i l t t l t t l i i l
? 3 CXA2542Q pin description pin no. symbol i/o equivalent circuit description 1 fei i 2 fdfct i focus error input. connects the capacitor for defect time constant. 3 fgd i ground this pin through a capacitor for cutting the focus servo high- frequency gain. 4 flb i external time constant setting pin for boosting the focus servo low- frequency. 5 fe_o o 12 ta_o o 15 sl_o o focus drive output. tracking drive output. sled drive output. 6 fe_m i focus amplifier inverted input. 1 4 7 5 0 k 9 0 k 2 6 2 5 0 5 1 2 1 5 1 4 7 1 0 0 k 1 4 7 2 3 1 1 4 7 1 3 0 k 6 8 k 4 4 0 k 4 7 0 k 3 3 0 k 3 4 7 srch i external time constant setting pin for generating focus search waveform. 1 4 7 5 0 k 1 1 2 0 k 7
? 4 CXA2542Q 8 tgu i external time constant setting pin for switching tracking high- frequency gain. 9 tg2 i external time constant setting pin for switching tracking high-frequency gain. 10 fset i peak frequency setting pin for focus and tracking phase compensation amplifier. 11 ta_m i tracking amplifier inverted input. 13 sl_p i 14 sl_m i sled amplifier non-inverted input. sled amplifier inverted input. 1 4 7 2 1 3 1 4 7 1 0 0 k 1 1 1 1 1 4 7 k 1 5 k 1 5 k 1 0 2 0 k 1 1 0 k 8 2 k 1 4 7 8 4 7 0 k 9 16 iset i connects the external capacitor to set the current which determines the focus search, track jump, and sled kick levels. 1 4 7 5 0 1 6 1 4 7 2 2 1 4 pin no. symbol i/o equivalent circuit description
? 5 CXA2542Q 18 clk i 20 data i 17 v cc i positive power supply. serial data input from cpu. (no pull-up resistance) serial data transfer clock input from cpu. (no pull-up resistance) 19 xlt i 21 xrst i latch input from cpu. (no pull-up resistance) reset input; resets at low. (no pull-up resistance) 1 4 7 2 0 1 k 1 8 2 0 1 4 7 2 0 4 k 2 . 5 p 1 9 2 1 22 c. out o 23 sens1 o 24 sens2 o track number count signal output. outputs fzc, dfct1, tzc, balh, tgh, foh, atsc, and others according to the command from cpu. outputs dfct2, mirr, ball, tgl, fol, and others according to the command from the cpu. 1 0 0 k 1 4 7 2 0 k 2 2 2 3 2 4 v c c 1 7 25 fok o focus ok comparator output. 1 4 7 2 0 k 1 0 0 k 4 0 k 2 5 pin no. symbol i/o equivalent circuit description
? 6 CXA2542Q 26 cc2 i 27 cc1 o 28 cb i input for the defect bottom hold output with capacitance coupled. defect bottom hold output. connected internally to the interruption comparator input. connects the defect bottom hold capacitor. 1 4 7 1 4 7 1 4 7 4 3 k 1 1 k 1 2 0 k 2 6 2 7 2 8 29 cp i connects the mirr hold capacitor. mirr comparator non-inverted input. 30 rf_i i 31 rf_o o 32 rf_m i 1 . 5 k 1 0 0 k 2 9 1 4 7 1 4 7 1 4 7 1 0 k 1 0 k 3 0 3 1 3 2 input for the rf summing amplifier output with capacitance coupled. rf summing amplifier output. eye- pattern check point. rf summing amplifier inverted input. the rf amplifier gain is determined by the resistance connected between this pin and rfo pin. 33 rftc i external time constant setting pin during rf level control. 1 4 7 5 0 1 0 5 0 3 3 pin no. symbol i/o equivalent circuit description
? 7 CXA2542Q 34 ld o apc amplifier output. 35 pd i apc amplifier input. 36 37 pd1 pd2 i i rf i-v amplifier inverted input. connect these pins to the photo diode a + c and b + d pins. 1 4 7 1 0 k 7 . 5 k 1 0 0 2 k 8 k 3 6 3 7 0 . 2 p 1 4 7 8 2 0 5 5 k 1 0 k 3 5 1 k 1 0 k 3 4 38 39 f e i i f i-v and e i-v amplifier inverted input. connects these pins to photo diodes f and e. 1 4 7 2 6 0 k 1 2 p 5 0 0 1 0 3 8 3 9 v e e 4 0 40 v ee negative power supply. pin no. symbol i/o equivalent circuit description
? 8 CXA2542Q 43 atsc i 44 tzc i window comparator input for atsc detection. tracking zero-cross comparator input. 41 teo o tracking error amplifier output. e-f signal is output. 45 tdfct i connects the capacitor for defect time constant. 1 4 7 7 5 k 1 0 4 4 1 4 7 1 k 1 0 0 k 1 0 0 k 1 k 1 0 1 0 4 3 42 lpfi i comparator input for balance adjustment. (input from teo through lpf) 1 4 7 7 4 2 1 4 7 3 2 k 1 5 k 3 k 1 5 k 2 0 k 1 5 0 k 1 5 0 k 6 . 6 k 1 4 7 1 0 0 k 3 4 1 4 5 pin no. symbol i/o equivalent circuit description
? 9 CXA2542Q 46 vc o (v cc + v ee )/2 direct voltage output. v c 5 0 1 2 0 1 2 0 1 6 k 1 0 k 4 6 47 fzc i focus zero-cross comparator input. 1 4 7 1 0 7 5 k 9 k 5 1 k 4 7 48 feo o focus error amplifier output. connected internally to the window comparator input for bias adjustment. 1 4 7 2 5 p 1 7 4 k 1 0 1 0 3 0 0 4 8 pin no. symbol i/o equivalent circuit description
? 10 CXA2542Q test t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 current consumption 1 current consumption 2 center amplifier output offset offset voltage gain max. output amplitude - high max. output amplitude - low offset voltage gain 1 voltage gain 2 voltage gain difference max. output voltage ?high max. output voltage ?low bias0 bias1 bias2 bias3 bias4 bias5 bias6 19 (off) 19 (off) 19 (off) 10, 13 10, 13 10, 13 10 13 13 10 rst rst rst rst rst rst rst 39f 39f 39f 39f 39f 39f 3bf 3be 3bd 3bb 3b7 3af 39f 17 40 36 37 36 37 36 37 36 37 37 36 17 40 46 31 31 31 31 48 48 48 48 48 48 48 48 48 48 48 48 1khz i/o ratio v2 = 0.2vdc v2 = 0.2vdc 1fb6: on 1khz i/o ratio 1khz i/o ratio v2 = 100mvdc v2 = 100mvdc ifb1, 2, 3, 4, 5, 6: off ifb1: on, bias0: reference ifb2: on, bias0: reference output gain difference with t15 ifb3: on, bias0: reference output gain difference with v17 ifb4: on, bias0: reference output gain difference with v18 ifb5: on, bias0: reference output gain difference with v19 ifb6: on, bias0: reference output gain difference with v20 12.2 ?5.4 ?00 ?0 24.5 1.2 ?20 26 26 ? 1 560 ?9.0 5 5 5 5 5 18.8 ?8.8 0 0 27.5 1.3 ?.6 0 29 29 0 1.3 ?.3 718 ?2.7 6 6 6 6 6 25.4 ?2.2 100 50 30.5 ?.3 120 32 32 3 ? 1042 ?6.5 7 7 7 7 7 ma ma mv mv db v v mv db db db v v mv mv db db db db db item sw conditions (on switches) sd input pin measurement conditions min. typ. max. unit electrical characteristics (v cc = 1.5v, v ee = 1.5v, topr = 25 c) rf amplifier fe amplifier measure- ment pin
? 11 CXA2542Q foh threshold fol threshold offset gain up (f) gain up (e) voltage gain f0 voltage gain f1 voltage gain f2 voltage gain f3 voltage gain f4 voltage gain e0 voltage gain e1 voltage gain e2 voltage gain e3 voltage gain e4 max. output voltage ?high max. output voltage ?low output voltage 1 output voltage 2 output voltage 3 output voltage 4 ld off t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 t34 t35 t36 t37 t38 t39 t40 t41 t42 14 15 14 14 14 14 14 15 15 15 15 15 1 1 9 38 39 38 39 38 38 38 38 38 39 39 39 39 39 38 39 35 35 35 35 35 39f 39f 34f 308 36f 308 36f 308 34f 34e 30f 34d 34b 347 34f 30f 00 30e 30d 30b 307 34f 308 34f 308 3c4 3c4 3c4 3c4 3c0 48 48 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 34 34 34 34 34 i fb6: on pin 1 voltage when sens1 (pin 23) goes from high to low ifb6: on pin 1 voltage when sens2 (pin 24) goes from high to low tog: off, bal1, 2, 3: on v1 = 2 khz, i/o ratio tog: off, bal1, 2, 3: on v1 = 2 khz, i/o ratio tog: off, bal1, 2, 3: on v1 = 2khz, tog: off i/o ratio v1 = 2khz, tog1: on reference to f0 v1 = 2khz, tog2: on reference to f0 v1 = 2khz, tog3: on reference to f0 v1 = 2khz, tog4: on reference to f0 v1 = 2khz, bal: off i/o ratio v1 = 2khz, bal1: on reference to e0 v1 = 2khz, bal2: on reference to e0 v1 = 2khz, bal3: on reference to e0 v1 = 2khz, bal4: on reference to e0 v1 = 1vdc, tog: off, bal1, 2, 3: on v1 = 1vdc, tog: off, bal1, 2, 3: on i1 = 364 a i1 = 439 a i1 = 515 a 0.8ma sink i1 = 515 a, ld: off 5 ?5 ?5 7.2 7.2 1.2 ?.3 ?.9 ?.9 ?1.1 ?.6 0.16 0.58 1.43 2.96 0.5 ?00 ?93 163 ?00 1.1 20 ?0 0 10.2 10.2 4.2 ?.8 ?.4 ?.4 ?0.6 1.4 0.46 0.88 1.73 3.26 0.7 ?.8 ?04 ?93 613 132 1.3 35 ? 25 13.2 13.2 7.2 ?.3 ?.9 ?.9 ?0.1 4.4 0.76 1.18 2.03 3.56 ?.5 ?00 107 1063 500 mv mv mv db db db db db db db db db db db db v v mv mv mv mv v fe amplifier te amplifier apc test item sw conditions (on switches) sd input pin measure- ment pin measurement conditions min. typ. max. unit
? 12 CXA2542Q t43 t44 t45 t46 t47 t48 t49 t50 t51 t52 t53 t54 t55 t56 t57 t58 t59 t60 t61 t62 t63 t64 50% limit 17% limit ?0% limit ?7% limit direct voltage gain fcs total gain feed through 1 fzc threshold max. output voltage ?high max. output voltage ?low search voltage (? search voltage (+) direct voltage gain trk total gain feed through 1 max. output voltage ?high max. output voltage ?low jump output voltage (? jump output voltage (+) atsc threshold (? atsc threshold (+) tzc threshold 8 8 10, 13 10, 13 1 1 18 1 1 5, 17 5, 17 18 3c7 3c5 3c7 3c5 08 00 08 00 08 08 02 03 25 20 25 20 25 20 25 2c 28 10 10 20 35 30 35 30 35 36 37 35 36 37 1 1 47 1 1 38 38 38 38 43 43 44 34 34 34 34 5 5 47 5 5 5 5 12 12 12 12 12 12 43 43 44 i1 = 273 a output difference with lpc on/off i1 = 394 a output difference with lpc on/off i1 = 742 a output difference with lpc on/off i1 = 621 a output difference with lpc on/off t9 + t47 i/o gain difference between sd = 00 and sd = 08. pin 47 voltage when sens1 (pin 23) goes from low to high v1 = 200mvdc v1 = ?00mvdc dc gain between teo and ta_o t26 + t55 output gain difference between sd = 20 and sd = 25. v1 = ?.3vdc v1 = 0.3vdc input voltage when tg2 (pin 9) goes from vcc/2 to vcc input voltage when tg2 (pin 9) goes from vcc/2 to vcc pin 44 voltage when sens1 (pin 23) is 0v 725 476 ?421 ?03 17.4 47.9 191 1 ?21 399 11.4 16.8 1 ?52 437 ?5 7 ?0 1330 886 ?16 ?93 20.9 49.9 231 1.3 ?.3 ?81 539 14.6 18.8 1.3 ?.3 ?12 577 ?5 15 0 1935 1296 ?11 17 24.4 51.9 ?0 271 ? ?41 679 17.8 20.8 ?9 ? ?72 717 ? 25 20 mv mv mv mv db db db mv v v mv mv db db db v v mv mv mv mv mv rf level controll focus servo tracking servo test item sw conditions (on switches) sd input pin measurement conditions min. typ. max. unit measure- ment pin
? 13 CXA2542Q t65 t66 t67 t68 t69 t70 t71 t72 t73 t74 t75 t76 t77 t78 t79 t80 t81 t82 bal comp threshold ?high bal comp threshold ?low gain comp threshold ?high gain comp threshold ?low fok threshold voltage gain feed through max. output voltage ?high max. output voltage ?low kick voltage 1 kick voltage 2 max. operating frequency 1 min. input operating voltage 1 max. input operating voltage 1 min. operating frequency 1 max. operating frequency 1 min. input operating voltage 1 max. input operating voltage 1 16 16 14 14 8 6, 7 6 6 6 8 8 8 10, 11, 12, 13 10, 11, 12, 13 10, 11, 12, 13 10, 11, 12, 13 300 300 308 34f 308 34f 25 20 25 25 25 20 20 20 20 20 10 10 10 10 42 42 38 38 30 13 13 13 13 30 30 30 36 37 36 37 36 37 36 37 42 42 41 41 25 15 15 15 15 15 15 24 24 24 23 23 23 23 pin 42 voltage when sens1 (pin 23) goes from high to low pin 42 voltage when sens2 (pin 24) goes from high to low pin 41 voltage when sens1 (pin 23) goes from high to low pin 41 voltage when sens2 (pin 24) goes from low to high pin 30 voltage when pin 25 is 0v v1 = 100hz, i/o ratio output gain difference between sd = 20 and sd = 25. v1 = 400mvdc v1 = 400mvdc rev 1 fwd 1 measures at sens2 pin. measures at sens2 pin. measures at sens2 pin. measures at sens1 pin. measures at sens1 pin. measures at sens1 pin. measures at sens1 pin. 5 ?5 168 127 ?00 50 1 ?50 450 30 1.8 2.5 1.8 20 ?0 193 145 ?67 1.3 ?.3 ?00 600 35 ? 218 163 ?30 ?4 ? ?50 750 0.3 1 0.5 mv mv mv mv mv db db v v mv mv khz vp-p vp-p khz khz vp-p vp-p tracking servo fok sled servo mirror defect test item sw conditions (on switches) sd input pin measurement conditions min. typ. max. unit measure- ment pin
? 14 CXA2542Q g n d r 1 9 1 0 k c 4 0 . 1 s 3 s 2 r 9 4 7 k c 3 1 0 0 0 p s 1 c 1 1 0 0 0 p s 1 9 s 1 6 v 2 a c d c i 2 0 . 8 m a c 5 1 r 1 3 2 2 k s 8 c 7 0 . 0 1 c 9 3 3 0 0 p s 7 r 2 5 1 3 k s 6 c 1 1 4 7 r 2 3 6 0 k r 3 1 0 k v 1 a c d c g n d c 2 3 3 g n d s 1 7 g n d s 1 8 g n d g n d g n d s 2 0 g n d g n d v e e g n d r 1 3 9 0 k s 1 5 r 2 3 9 0 k s 1 4 g n d g n d g n d g n d r 1 1 1 3 k g n d r 1 2 1 0 0 k s 5 r 1 5 1 0 k v c c r 1 6 5 1 0 k v c c c 8 0 . 0 1 r 1 8 1 3 k g n d r 1 7 1 0 0 k g n d r 2 4 5 . 1 k g n d g n d v e e r 2 6 1 2 0 k v c c g n d c l k c 1 0 3 3 x l t d a t a x r s t v c c r 2 0 1 0 k v c c r 2 1 1 0 k v c c r 2 2 1 0 k v c c g n d c 6 0 . 0 1 g n d g n d r 1 4 1 0 k r 1 0 1 m v e e v c c r 8 3 3 0 v e e v c c i 1 0 a g n d f e v e e t e o l p f i a t s c t z c t d f c t v c s e n s 1 c . o u t x r s t d a t a x l t c l k v c c i s e t s l _ o s l _ m s l _ p s e n s 2 f z c 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 3 9 3 8 3 7 4 1 4 2 4 5 4 6 4 7 4 0 4 4 4 3 f d f c t f g d f l b f e _ o f e _ m s r c h t g u t g 2 f s e t t a _ m t a _ o f e i p d 1 p d l d r f _ m r f _ o r f _ i c p c b c c 1 f o k r f t c c c 2 p d 2 f e o 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 2 5 2 6 2 7 2 8 2 9 3 0 3 6 3 5 3 4 3 1 3 2 3 3 4 8 r 5 2 4 0 k r 6 2 4 0 k s 1 1 s 1 2 r 4 1 0 k r 7 1 0 k s 1 3 a a a a a a a a a a s 1 0 s 9 r 2 6 1 0 0 k electrical characteristics measurement circuit
? 15 CXA2542Q application circuit 1 ( 2.5v power supply) p d 1 p d l d r f _ m r f _ o r f _ i c p c b c c 1 f o k r f t c c c 2 v c c m i c r o c o m p u t e r d s p 1 5 k 2 2 3 . 3 d r i v e r 1 0 0 k 0 . 0 1 5 6 0 k v e e v e e 1 0 0 k 1 5 0 k 0 . 0 4 7 0 . 1 f e v e e t e o l p f i a t s c t z c t d f c t v c 8 2 k f e 8 . 2 k s e n s 1 c . o u t x r s t d a t a x l t c l k v c c i s e t s l _ o s l _ m s l _ p s e n s 2 4 7 k 3 3 0 k 4 7 0 p 0 . 0 2 2 0 . 0 2 2 f z c 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 3 9 3 8 3 7 4 1 4 2 4 5 4 6 4 7 4 0 4 4 4 3 0 . 0 1 0 . 0 1 0 . 1 6 8 0 k 5 1 0 k 0 . 0 1 5 2 2 0 0 p 0 . 1 0 . 1 1 0 0 k 4 . 7 d r i v e r 0 . 0 3 3 v c c 1 0 0 k d r i v e r 1 0 k 1 0 k 0 . 0 3 3 0 . 0 1 0 . 0 3 3 0 . 0 1 2 2 k v c c 2 2 1 0 0 1 1 0 h 1 0 0 5 0 0 v e e v c c 1 k 3 . 3 a c b d p d l d 1 m 1 v e e v e e f d f c t f g d f l b f e _ o f e _ m s r c h t g u t g 2 f s e t t a _ m t a _ o f e i p d 2 f e o 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 2 5 2 6 2 7 2 8 2 9 3 0 3 6 3 5 3 4 3 1 3 2 3 3 4 8 application circuit 2 (single +5v power supply) v c c m i c r o c o m p u t e r d s p 1 5 k 2 2 3 . 3 d r i v e r 1 0 0 k 0 . 0 1 5 6 0 k 1 0 0 k 1 5 0 k 0 . 0 4 7 0 . 1 f e v e e t e o l p f i a t s c t z c t d f c t v c 8 2 k f e 8 . 2 k s e n s 1 c . o u t x r s t d a t a x l t c l k v c c i s e t s l _ o s l _ m s l _ p s e n s 2 4 7 k 3 3 0 k 4 7 0 p 0 . 0 2 2 0 . 0 2 2 f z c 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 3 9 3 8 3 7 4 1 4 2 4 5 4 6 4 7 4 0 4 4 4 3 0 . 0 1 0 . 0 1 0 . 1 6 8 0 k 5 1 0 k 0 . 0 1 5 2 2 0 0 p 0 . 1 0 . 1 1 0 0 k 4 . 7 d r i v e r 0 . 0 3 3 v c c 1 0 0 k d r i v e r 1 0 k 1 0 k 0 . 0 3 3 0 . 0 1 0 . 0 3 3 0 . 0 1 2 2 k v c c 2 2 1 0 0 1 1 0 h 1 0 0 5 0 0 v c c 1 k 3 . 3 a c b d p d l d 1 m 1 f d f c t f g d f l b f e _ o f e _ m s r c h t g u t g 2 f s e t t a _ m t a _ o f e i p d 1 p d l d r f _ m r f _ o r f _ i c p c b c c 1 f o k r f t c c c 2 p d 2 f e o 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 2 5 2 6 2 7 2 8 2 9 3 0 3 6 3 5 3 4 3 1 3 2 3 3 4 8 v c c 1 0 1 0 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 16 CXA2542Q description of functions rf amplifier the photodiode currents input to the input pins (pd1 and pd2) are each i-v converted through a 58k equivalent resistor by the pd i-v amplifiers. these signals are added by the rf summing amplifier, and the photodiode (a + b + c + d) current-voltage converted voltage is output to the rfo pin. an eye-pattern check can be performed at this pin. the low frequency component of the rfo output voltage is v rfo = ?.2 (v a + v b ) = 127.6k (ipd1 + ipd2). 1 k 3 . 3 a c b d p d 1 i p d 1 ? p d 2 i p d 2 ? 5 8 k v a 1 0 k v c p d 1 i v a m p 5 8 k v b 1 0 k v c p d 2 i v a m p r f _ m r f _ o 2 2 k v c r f s u m m i n g a m p 3 2 3 1 3 6 3 7
? 17 CXA2542Q focus error amplifier f e o f e i f e _ o f e _ m p d 2 p d 1 s e n s 1 s e n s 2 r 8 1 0 0 k v e e 2 0 m v f o c u s p h a s e c o m p e n s a t i o n s e n s s e l e c t o r v h v i n > v h l v i n < v h h f o h 2 0 m v v l v i n > v l h v i n < v l l f o l v c v c v c r 1 1 1 0 0 k d r i v e r g n d g n d c 1 2 2 0 0 p r 9 1 0 k r 1 0 1 0 k r 1 1 6 k v c v c r 4 3 2 k r 2 5 8 k v c c r 7 1 7 4 k v c r 5 3 2 k r 3 5 8 k p d 2 i v a m p p d 1 i v a m p i f b 6 3 2 i f b 5 1 6 i f b 4 8 i f b 3 4 i f b 2 2 i f b 1 1 r e s e t : i f b 1 t o i f b 6 o n 2 5 m v / s t e p b + d a + c v i n r 6 1 7 4 k v a v b f e a m p 4 8 1 6 5 2 3 2 4 3 2 3 7 3 6 the focus error amplifier calculates the difference between output va and vb of the rf i-v amplifier, and output current-voltage converted voltage of the photodiode (a + c ?b ?d). the feo output voltage: 174k v feo = 32k (va ?vb) 174k = 32k {(?8k ipd1) ?(?8k ipd2)} = 315.4k (ipd2 ?ipd1) the focus error amplifier has a built-in bias adjustment circuit to enable software-based automatic adjustment. the focus bias adjustment is performed by turning the focus bias adjustment switches (ifb1 to ifb6) on and off. the 6-bit focus bias adjustment switches are controlled with commands. ifb1 to ifb6 are all on after a reset. the voltage is varied by approximately 25mv per step.
? 18 CXA2542Q focus error amplifier offset adjustment (when adjusting the ic offset) the offset adjustment is performed by comparing the feo when the focus servo is off with the reference level. the feo and reference level are compared by the window comparator, and the comparison results are output from sens1 and sens2. (address d11 001110 d6 ) adjust the offset so that sens1 and sens2 are both high. set the reference level to the center 20mv. 25mv < 40mv < 50mv reference level width variable voltage per step variable voltage per 2 steps focus bias fine adjustment fine adjustment is performed by turning the focus bias adjustment switches (ifb1 to ifb6) on and off while monitoring a dsp jitter meter with the microcomputer. the 6-bit focus bias adjustment switches are controlled with commands. when performing conventional focus bias adjustment fix the focus bias adjustment switches to the desired settings. (for example, ifb6 on) in this condition, adjust the focus bias by turning a volume connected to fe_bias (pin 40).
? 19 CXA2542Q the difference between e i-v amplifier output ve and f i-v amplifier output vf is taken and output from teo. the tracking error amplifier has built-in balance and gain adjustment circuits to enable software-based automatic adjustment. the balance adjustment is performed by varying the combined resistance value of the t-configured feedback resistance at the e i-v amplifier. e i-v amp feedback resistance = r1 + r4 + f i-v amp feedback resistance = r2 + r5 + = 403k vary the combined resistance value of the e i-v amplifier's feedback resistance by using the balance adjustment switches (bal1 to bal4). the gain adjustment is performed by resistance dividing the te amp output by the gain adjustment switches (tog1 to tog4). the balance and gain adjustment switches are controlled with commands. set the cut-off frequency of the external lpf between 10hz to 100hz. tracking error amplifier l p f i t e o f c l k d a t a x r s t x l t s e n s 1 s e n s 2 v i n > v h l v i n < v h h b a l h v h 2 0 m v v c v i n 2 0 m v v c v l v i n > v l h v i n < v l l b a l l v i n > v h l v i n < v h h t g h v h 2 0 0 m v v c v i n 1 5 0 m v v c v l v i n > v l h v i n < v l l t g l s e n s s e l e c t o r c o m a n d c o n t r o l c p u r 2 3 1 0 0 k r 2 4 1 5 0 k c 3 0 . 0 1 c 4 0 . 0 1 g n d g n d v c r 2 1 6 . 6 k r 2 0 1 5 k r 1 9 3 2 k r 1 7 2 0 k r 2 2 3 k r 1 8 1 5 k r 1 6 9 6 k t e a m p n o r m a l r 1 4 1 3 k r 9 1 7 k g a i n u p g a i n u p r 8 1 7 k v c r 1 2 9 6 k r 1 3 1 3 k v n o r m a l t g f l t g f l c 2 1 2 p r 2 2 6 0 k r 5 1 3 k r 3 2 6 k v c v c c 1 1 2 p r 1 2 6 0 k r 4 6 . 8 k v c e v f v e f i - v a m p e i - v a m p r 7 1 1 0 k r 1 0 5 6 k r 1 1 2 7 k r 1 5 1 3 k r 6 7 5 k r e v c + 2 3 4 1 4 2 c o m a n d c o n t r o l b a l 1 b a l 2 b a l 3 b a l 4 t o g 4 t o g 3 t o g 2 t o g 1 3 8 3 9 2 4 2 1 2 0 1 9 1 8 r1 r4 re r2 r5 r3
? 20 CXA2542Q balance adjustment the balance adjustment is performed by passing the tracking error signal (teo signal) through the external lpf, extracting the offset dc, and comparing it to the reference level. however, the teo signal frequency distribution ranges form dc to 2khz. merely sending the signal through the lpf leaves lower frequency components, and the complete offset dc can not be extracted. to extract it, monitor the teo signal frequency at all times, and perform adjustment only when a frequency that can lower a sufficient gain appears on the lpf. use the c.out output to check this frequency. the offset dc and reference level are compared by the window comparator. the comparison signal is output from the sens1 and sens2 pins. (address d11 001100 d6 ) adjust the balance so that the sens1 and sens2 pins are both high. gain adjustment gain adjustment is performed by passing the teo signal through the hpf and comparing the ac component to the reference level. the ac component is generated by taking the difference between te and the offset dc input to pin 42. the ac component and reference level are compared by the window comparator. the comparison signal is output from the sens1 and sens2 pins. (address d11 001101 d6 ) the comparison signal is as follows. sens1 pin balh sens2 pin ball h l h h l h v in < v l < v h v l < v in < v h v l < v h < v in v h : high level threshold value v in : window comparator input signal v l : low level threshold value s e n s 1 p i n t g h h h l s e n s 1 p i n t g l v h v l v i n ( 1 ) ( 2 ) ( 3 ) the gain should be adjusted so that the sens1 and sens2 pins are as shown in status (2). when the teo signal level is low and tgh (sens1 pin) does not go low, the gain should be raised with the tgfl command for adjustment. if the adjustment does not bring the result of low, check the pulse duty of tgl (sens2 pin).
? 21 CXA2542Q apc & laser power control l d r f t c r f _ o r f _ i p d v e e v c c r 8 1 0 k v e e r 5 5 5 k r 1 0 5 6 k r 1 2 5 6 k r 1 1 1 0 k r 4 1 0 k r 6 1 k l d o n r 1 4 1 2 . 5 k v l v r e f l p c o n / o f f 5 0 % / 1 7 % 6 7 0 m v r 9 2 3 . 5 k v c r 7 3 9 . 5 k v c r f 1 . 4 7 v 1 . 1 v p p r 1 3 1 m v e e v e e c 4 1 r 1 2 2 c 2 1 0 0 c 1 1 v e e r 3 1 0 0 r 2 5 0 0 1 3 0 m v g n d l d p d l 1 1 0 h v c c c 3 0 . 0 1 3 0 3 1 3 3 3 4 3 5 apc when the laser diode is driven by a constant current, the optical power output has extremely large negative temperature characteristics. the apc circuit is used to maintain the optical power output at a constant level. the laser diode current is controlled according to the monitor photodiode output. laser power control the rf level is stabilized by attaching an offset to the apc v l and controlling the laser power in sync with the rf level fluctuations. the rf_o and rf_i levels are compared and the larger of the two is smoothed by the rftc's external cr. this signal is then compared with the reference level. the laser power is controlled by attaching an offset to v l according to the results of comparison with the reference level. set the reference level to 670mv. (center voltage reference) lpc on/off and ld on/off control is performed with commands. the laser power control limit can also be switched between 50% and 17% with commands. lpc off on on 50% 17% approximately 1.27v approximately 1.27v 625mv approximately 1.27v 208mv lpcl v l variable range
? 22 CXA2542Q center voltage generation circuit (the figure below shows a single voltage application; connect to gnd for dual power supplies.) maximum current is approximately 3ma. output impedance is approximately 50 . 5 0 v c c v e e v c c o n n e c t e d i n t e r n a l l y t o t h e v e e p i n . 3 0 k 3 0 k v c c g n d v c 4 6
? 23 CXA2542Q focus servo 9 k 5 1 k f e 2 2 0 0 p 1 0 k f e o f e i 1 0 0 k d f c t f s 4 f o c u s p h a s e c o m p e n s a t i o n 6 8 k 1 0 0 k f e _ o f o c u s c o i l f e _ m 1 0 0 k i s e t 6 0 k 1 1 2 2 f s 2 f s 1 5 0 k 5 0 k 4 . 7 0 . 0 1 5 5 1 0 k 0 . 1 f s e t f l b 4 0 k 0 . 1 0 . 1 6 8 0 k f d f c t f g d s r c h s e n s s e l e c t o r f s 3 1 0 k 0 . 0 2 2 f z c 7 5 k f z c s e n s 1 c h a r g e u p 4 7 4 8 1 2 3 4 1 0 7 1 6 6 5 2 3 the above figure shows a block diagram of the focus servo. ordinarily the fe signal is input to the focus phase compensation circuit through a 68k resistance; however, when dfct is detected, the fe signal is switched to pass through a low-pass filter formed by the internal 100k resistance and the capacitance connected to pin 2. when this dfct prevention circuit is not used, leave pin 2 open. the defect switch operation can be enabled and disabled with command. the capacitor connected between pin 4 and gnd is a time constant to boost the low frequency in the normal playback state. the peak frequency of the focus phase compensation is approximately 1.2khz when a resistance of 510k is connected to pin 10. the focus search height is approximately 1.1vp-p when using the constants indicated in the above figure. this height is inversely proportional to the resistance connected between pin 17 and v ee . however, changing this resistance also changes the height of the track jump and sled kick as well. the fzc comparator inverted input is set to 15% of vcc and vc (pin 46); (vcc ?vc) 15%. * 510k resistance is recommended for pin 10.
? 24 CXA2542Q tracking and sled servo + t e t e o b u f f e r a m p l p f i 0 . 0 1 0 . 0 1 1 5 0 k 1 0 0 k d f c t 1 0 0 k t d f c t 0 . 1 a t s c 4 7 0 p 3 3 0 k 4 7 k 0 . 0 4 7 0 . 0 2 2 t z c t z c t g u t g 2 0 . 0 3 3 4 7 0 k t g 2 2 0 k 5 1 0 k 0 . 0 1 5 f s e t t r a c k i n g p h a s e c o m p e n s a t i o n 1 0 k 9 0 k t m 4 t m 3 1 1 a 1 1 a 1 0 0 k t r a c k i n g c o i l 8 2 k 1 5 k 2 2 3 . 3 s l _ p t m 2 t m 6 t m 5 2 2 a 2 2 a 1 0 0 k 1 k 1 k 1 0 0 k a t s c 8 . 2 k 1 2 0 k 0 . 0 1 5 m s l e d m o t o r s l _ o s l _ m t m 1 6 8 0 k 6 8 0 k 6 6 p t a _ m t a _ o t g 1 t m 7 g a i n w i n d o w c o m p a r a t o r b a l a n c e w i n d o w c o m p a r a t o r s e n s s e l e c t o r b a l h b a l l t g h t g l s e n s 1 s e n s 2 t e 2 4 2 3 1 5 1 4 1 3 1 1 1 2 1 0 9 8 4 4 4 3 4 5 4 2 4 1 the above figure shows a block diagram of the tracking and sled servo. the capacitor connected between pins 8 and 9 is a time constant to cut the high-frequency gain when tg2 is off. the peak frequency of the tracking phase compensation is approximately 1.2khz when a 510k resistance is connected to pin 10. in the CXA2542Q, tg1 and tg2 are inter-linked switches. to jump tracks in fwd and rev directions, turn tm3 or tm4 on. during this time, the peak voltage applied to the tracking coil is determined by the tm3 or tm4 current and the feedback resistance from pin 11. to be more specific, track jump peak voltage = tm3 (or tm4) current feedback resistance value the fwd and rev sled kick is performed by turning tm5 or tm6 on. during this time, the peak voltage applied to the sled motor is determined by the tm5 or tm6 current and the feedback resistance from pin 14; sled kick peak voltage = tm5 (or tm6) current feedback resistance the values of the current for each switch are determined by the resistance connected between pin 16 and v ee . when this resistance is 60k : tm3 (or tm4) = 11 a, and tm5 (or tm6) = 22 a. as is the case with the fe signal, the te signal is switched to pass through a low-pass filter formed by the internal resistance (100k ) and the capacitance connected to pin 45.
the iset pin is used to connect external resistance. this external resistance sets the current which determines the focus search, track jump, and sled kick heights. focus search current i 1 = (v bg : approximately 1.27v) i 2 = 2i 1 track jump current (tm3 and tm4 current) i = sled kick current (tm5 and tm6 current, when d1 = d0 = 0 during 1x$ commands) i = use external resistance of between 30k to 240k . using external resistance outside this range may cause oscillation. ? 25 CXA2542Q f s 1 i 2 i 1 v bg r 1 2 v bg r v bg r 1 2
? 26 CXA2542Q focus ok circuit r f 1 5 k 9 2 k v g 5 4 k 2 0 k v c c 0 . 6 3 v r f _ o r f _ i f o k 1 f o c u s o k a m p f o c u s o k c o m p a r a t o r c 5 0 . 0 1 3 1 3 0 2 5 the focus ok circuit creates the timing window okaying the focus servo from the focus search state. the hpf output is obtained at pin 30 from pin 31 (rf signal), and the lpf output (opposite phase) of the focus ok amplifier output is also obtained. the focus ok output is inverted when v rfi ?v rfo ?.37v. note that, c5 determines the time constant of the hpf for the mirror circuit and the lpf of the focus ok amplifier. ordinarily, with a c5 equal to 0.01 f selected, the fc is equal to 1khz, and block error rate degradation brought about by rf envelope defects caused by scratched discs can be prevented. defect circuit after inversion, rf_o signal is bottom held by means of the long and short time constants. the long time- constant bottom hold keeps the mirror level prior to the defect. the short time-constant bottom hold responds to a disc mirror defect in excess of 0.1ms, and this is defferentiated and level-shifted through the ac coupling circuit. the long and short time-constant signals are compared to generate at mirror defect detection signal. r f _ o a 2 b d e f e c t a m p c c 1 c c 2 s e n s 1 c b 0 . 0 1 0 . 0 3 3 d e f e c t s w d e f e c t c o m p a r a t o r d e f e c t b o t t o m h o l d e c d 2 6 2 8 s e n s 2 s e n s s e l e c t o r d f c t 1 f l i p f l o p d f c t 2 2 7 2 4 2 3 3 1 i n t e r r u p t i o n c o m p a r a t o r f e d c b a b o t t o m h o l d ( 1 ) s o l i d l i n e d e f e c t a m p r f o d f c t 1 b o t t o m h o l d ( 2 ) s o l i d l i n e h l f i n t h l
? 27 CXA2542Q mirror circuit the mirror circuit performs peak and bottom hold after the rfi signal has been amplified. the peak and bottom holds are both held through the use of a time constant. for the peak hold, a time constant can follow a 30khz traverse, and, for the bottom hold, one can follow the rotation cycle envelope fluctuation. the dc playback envelope signal j is obtained by amplifying the difference between the peak and bottom hold signals h and i. signal j has a large time constant of 2/3 its peak value, and the mirror output is obtained by comparing it to the peak hold signal k. accordingly, when on the disc track, the mirror output is low; when between tracks (mirrored portion), it is high; and when a defect is detected, it is high. the mirror hold time constant must be sufficiently large compared with the traverse signal. r f 0 . 0 3 3 r f _ o r f _ i c p m i r r o r c o m p a r a t o r p e a k & b o t t o m h o l d 1 . 4 k m i r r o r h o l d a m p j h i 1 g m i r r o r a m p s e n s s e l e c t o r m i r r s e n s 2 3 1 3 0 2 9 2 4 r f _ o h l 0 v 0 v 0 v 0 v g ( r f _ i ) h ( p e a k h o l d ) i ( b o t t o m h o l d ) ( m i r r o r h o l d ) j k m i r r
? 28 CXA2542Q sens selector s e n s 1 f z c d f c t 1 t z c b a l h t g h f o h a t s c s e n s 2 h i g h - z d f c t 2 m i r r b a l l t g l f o l 2 3 2 4 what is output to the sens1 and sens2 pins varies according to the address input to the data pin. data (pin 20) 8-bit transfer sens1 sens2 address d7 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 1 0 0 1 x x x x x x x x x x x x x x x x x x x x fzc dfct1 tzc h (high-z) h (high-z) dfct2 mirr h (high-z) d6 d5 d4 d3 d2 d1 d0 data data (pin 20) 12-bit transfer sens1 sens2 address d11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 x x x x x x x x x x x x x x x x x x x x x x x x balh tgh foh atsc ball tgl fol h (high-z) d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 data notes) 12-bit transfer should be performed during $3xx commands. when 8 bits are transferred, sens1 and sens2 are switched according to the d3 and d2 data. sens1 and sens2 are switched without latching.
? 29 CXA2542Q commands the input data to operate this ic is configured as 8-bit/12-bit data; however, below, this input data is represented by 2-digit hexadecimal numerals in the form $xx, where x is a hexadecimal numeral between 0 and f/$xxx for 12-bit. commands for the CXA2542Q can be broadly divided into four groups ranging in value from $0x, $1x, $2x, $3xx. 1. $0x (fzc at sens1 pin (pin 23), h (hi-z) at sens2 pin (pin 24)) these commands are related to focus servo control. the bit configuration is as shown below. d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 fs4 fs2 fs1 four focus related switches exist: fs1, fs2, fs4 and dfct. $00 when fs1 = 0, pin 7 is charged to (22 a ?11 a) 50k = 0.55v. if, in addition, fs2 = 0, this voltage is no longer transferred, and the output at pin 5 becomes 0v. $02 from the state described above, the only fs2 becomes 1. when this occurs, a negative signal is output to pin 5. this voltage level is obtained by equation 1 below. (22 a ?11 a) 50k .... equation 1 the srch down speed can be increased by the charge up circuit. $03 from the state described above, fs1 becomes 1, and a current source of +22 a is split off. then, a cr charge/discharge circuit is formed, and the voltage at pin 7 decreases with the time as shown in fig. 1 below. fig. 1. voltage at pin 7 when fs1 goes from 0 ? 1 this time constant is obtained with the 50k resistance and an external capacitor. by alternating the commands between $02 and $03, the focus search voltage can be constructed. (fig. 2) fig. 2. constructing the search voltage by alternating between $02 and $03. (voltage at pin 5) resistance between pins 5 and 6 50k 0 v 0 v $ 0 0 0 2 0 3 0 2 0 3 0 0 0 2
? 30 CXA2542Q t h e i n s t a n t w h e n t h e s i g n a l i s b r o u g h t i n t o f o c u s . $ 0 8 $ 0 3 ( $ 0 0 ) $ 0 2 ( 2 0 m s ) ( 2 0 0 m s ) d r i v e v o l t a g e f o c u s e r r o r s e n s 1 ( f z c ) f o c u s o k * t h e b r o k e n l i n e s i n t h e f i g u r e i n d i c a t e t h e v o l t a g e a s s u m i n g t h e s i g n a l i s n o t i n f o c u s . 1-1. fs4 this switch is provided between the focus error input and the focus phase compensation, and is in charge of turning the focus servo on and off. $00 ? $08 focus off focus on 1-2. procedure of focus activation for description, suppose that the polarity is as described below. a) the lens is searching the disc from far to near; b) the output voltage (pin 5) is changing from negative to positive; and c) the focus s-curve is varying as shown below. fig. 3. s-curve the focus servo is activated at the operating point indicated by a in fig. 3. ordinarily, focus searching and the turning the focus servo switch on are performed during the focus s-curve transits the point a indicated in fig. 3. to prevent misoperation, this signal is anded with the focus ok signal. in this ic, fzc (focus zero cross) signal is output from the sens1 pin (pin 23) as the point a transit signal. in addition, focus ok is output as a signal indicating that the signal is in focus (can be in focus in this case). following the line of the above description, focusing can be well obtained by observing the following timing chart. t a fig. 4. focus on timing chart
? 31 CXA2542Q 2. $1x (dfct1 at sens1 pin (pin 23), dfct2 at sens2 pin (pin 24)) these commands deal with switching tg1/tg2, brake circuit on/off, and the sled kick output. the bit configuration is as follows: d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 1 tg1, tg2 break sled kick circuit height on/off on/off tg1, tg2, tm7 the purpose of tg1 and tg2 is to switch the tracking servo gain up/normal. tg1 and tg2 are interlinked switches. the brake circuit (tm7) is to prevent the frequently occurred phenomena where the merely 10-track jump has been performed actually though a 100-track jump was intended to be done due to the extremely degraded actuator settling caused by the servo motor exceeding the linear range after a 100 or 10-track jump. for the prevention method, when the actuator travels radially; that is, when it traverses from the inner track to the outer track of the disc and vice versa, the brake circuit utilizes the fact that the phase relationship between the rf envelope and the tracking error is 180 out-of-phase to cut the unneeded portion of the tracking error and apply braking. note that the time from the high to low transition of fzc to the time command $08 is asserted must be minimized. to do this, the software sequence shown in b is better than the sequence shown in a. f z c ? n o y e s f . o k ? n o t r a n s f e r $ 0 8 l a t c h f z c ? n o f . o k ? n o t r a n s f e r $ 0 8 l a t c h ( a ) ( b ) y e s y e s y e s fig. 5. poor and good software command sequences d1 (ps1) 0 0 1 1 d0 (ps0) 0 1 0 1 1 2 3 4 relative value sled kick height
? 32 CXA2542Q e d g e d e t e c t i o n w a v e f o r m s h a p i n g w a v e f o r m s h a p i n g e d g e d e t e c t i o n [ * b ] [ * e ] r f _ i t z c c x a 2 5 4 2 q ( l a t c h ) q d c k ( m i r r ) [ * c ] [ * f ] [ * g ] b r k d 2 t m 7 l o w : o p e n h i g h : m a k e [ * a ] [ * d ] [ * h ] 3 0 4 4 fig. 6. tm7 movement during braking operation f r o m i n n e r t o o u t e r t r a c k 0 v f r o m o u t e r t o i n n e r t r a c k ( " m i r r " ) ( " t z c " ) b r a k i n g i s a p p l i e d f r o m h e r e . [ * a ] [ * b ] [ * c ] [ * d ] [ * e ] [ * f ] [ * g ] [ * h ] fig. 7. internal waveform 3. $2x (tzc at sens1 pin (pin 23), mirr at sens2 pin (pin 24)) these commands deal with turning the tracking servo and sled servo on/off, and creating the jump pulse and fast forward pulse during access operations. d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 0 tracking sled control control 00 off 00 off 01 servo on 01 servo on 10 f-jump 10 f-fast forward 11 r-jump 11 r-fast forward tm1, tm3, tm4, tm2, tm5, tm6
? 33 CXA2542Q 4. $3xx these commands mainly control the balance and gain control circuit switches used during automatic tracking adjustment and the bias circuit switch used during automatic focus bias adjustment. in the initial resetting state, bal1 to bal4 switches and tog1 to tog4 switches are on. also, the ifb1 to 6 switches are on. balance adjustment the balance adjustment switches bal1 to bal4 can be controlled by setting d6 = 0 and d7 = 0. the switches are set using d0 to d3. at this time, sens1 outputs balh and sens2 outputs ball. data is set by specifying switch conditions d0 to d3 and sending a latch pulse with d6 = 0 and d7 = 0. sending a latch pulse with d6, d7 0 does not change the balance switch settings. s t a r t c . o u t i s t h e f r e q u e n c y h i g h e n o u g h ? s e n s 1 / 2 b a l a n c e o k ? a d j u s t m e n t c o m p l e t e d b a l 1 t o b a l 4 s w i t c h c o n t r o l y e s n o gain adjustment the gain adjustment switches tog1 to tog4 can be controlled by setting d6 = 1 and d7 = 0. these switches are set using d0 to d3. at this time, sens1 outputs tgh and sens2 outputs tgl. in a fashion similar to the method used with the balance adjustment, set the data by specifying switch conditions d0 to d3 and sending a latch pulse with d6 = 1 and d7 = 0. s t a r t s e n s 1 / 2 g a i n o k ? a d j u s t m e n t c o m p l e t e d t o g 1 t o t o g 4 s w i t c h c o n t r o l y e s n o balance adjustment gain adjustment
? 34 CXA2542Q focus bias adjustment the focus bias adjustment switches ifb1 to 6 can be controlled by setting d6 = 0 and d7 = 1. the switches are set using d0 to d5. at this time, sens1 outputs foh and sens2 outputs fol. data is set by specifying switch conditions d0 to d5 and sending a latch pulse with d6 = 0 and d7 = 1. s t a r t s e n s 1 / 2 b i a s o k ? a d j u s t m e n t c o m p l e t e d i f b 1 t o 6 s w i t c h c o n t r o l y e s n o focus bias adjustment method tgfl the tracking gain can be switched by setting d5 with d6 = 1 and d7 = 0. the tracking gain is gain up with d5 = 1 and normal gain with d5 = 0. the teo signal level can be made higher by approximately 6db for gain up. when the teo signal level is low and tgh (sens1 pin) does not go low during tracking adjustment, the gain should be raised with the tgfl command for adjustment. lpc the laser power control circuit can be turned on and off by setting d0 with d6 = 1 and d7 = 1. the circuit is on with d0 = 1 and off with d0 = 0. lpcl the laser power control limit can be switched between 17% and 50% by setting d1 with d6 = 1 and d7 = 1. the control limit is 17% with d1 = 0 and 50% with d1 = 1. ldon the laser diode can be turned on and off by setting d2 with d6 = 1 and d7 = 1. the laser diode is on with d2 = 1 and off with d2 = 0.
? 35 CXA2542Q atsc the anti-shock function can be controlled by setting d3 with d6 = 1 and d7 = 1. this function is disabled with d3 = 1 and enabled with d3 = 0. at this time, sens1 outputs atsc. even if atsc is disabled, atsc is output to sens1. when an anti-shock signal is generated during the enable status, tg1 and tg2 switch to gain up mode. (in the block diagram, tg1 is set to the side and tg2 is off. even if tg1 and tg2 are normal mode, they switch to gain up mode in conjunction with atsc.) when the anti-shock function is not used, pin 43 (atsc) should be connected to vc. rdfct2 dfct2 can be reset by setting d4 with d6 = 1 and d7 = 1. dfct2 is reset with d4 = 1. after a reset, high is held when dfct1 rises. during $1x commands, dfct2 is output from sens2. dfct2 operates even if dfct is disabled. whether or not dfct rises at the proper timing for the microcomputer can also be confirmed. int the interruption (scratched disc) countermeasure circuit can be set to operating status by setting d5 with d6 = 1 and d7 = 1. this circuit is enabled when d5 = 1 and disabled when d5 = 0. even if dfct1 does not rise, this circuit is effective for scratched discs which cause mirr to rise. when mirr rises, the dfct switch is routed through the low-pass filter. the interruption countermeasure circuit is forcibly turned off regardless of the command when the tracking gain is increased. (including when the gain is increased by atsc) even if dfct is disabled, the interruption countermeasure circuit operates when int is enabled.
? 36 CXA2542Q cpu serial interface timing chart t w c k d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 t w c k t s u 1 / f c k t h t c d t w l t d d a t a c l k x l t item clock frequency clock pulse width setup time hold time delay time latch pulse width data transfer interval low level input voltage high level input voltage symbol fck fwck t su t h t d t wl t cd v il v ih min. 500 500 500 500 1000 1000 0.0 (v cc ?v ee ) 0.9 typ. max. unit mhz ns ns ns ns ns ns v v 1 (v cc ?v ee ) 0.1 v cc (v cc = 3.0v)
? 37 CXA2542Q system control focus control tracking control tracking sled mode d7 d6 d5 d4 fs4 focus 1 = on 0 = off tg1, tg2 1 = gain up 0 = normal 0 0 0 0 0 0 0 0 1 0 1 0 brake 1 = enable 0 = disable fs2 srch on 1 = on 0 = off sled kick + 2 fs2 srch up 1 = up 0 = down sled kick + 1 fzc dfct1 tzc tracking mode * 1 sled mode * 2 address d3 d2 d1 d0 data data (pin 20) 8-bit transfer sens1 h (high-z) dfct2 mirr sens2 * 1 tracking mode fwd jump rev jump d3 0 0 1 1 d2 0 1 0 1 off on * 2 sled mode fwd move rev move d1 0 0 1 1 d0 0 1 0 1 off on item
? 38 CXA2542Q e-f balance tracking gain focus bias others d11 d10 d9 d8 dfct 1 = disable 0 = enable tgfl 1 = gain up 0 = normal ifb6 1 = off 0 = on int 1 = enable 0 = disable 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 d7 d6 ifb5 1 = off 0 = on rdfct2 1 = reset 0 = normal bal4 1 = off 0 = on tog4 1 = off 0 = on ifb4 1 = off 0 = on atsc 1 = disable 0 = enable bal3 1 = off 0 = on tog3 1 = off 0 = on ifb3 1 = off 0 = on ldon 1 = on 0 = off balh tgh foh atsc address d5 d4 d3 d2 bal2 1 = off 0 = on tog2 1 = off 0 = on ifb2 1 = off 0 = on lpcl 1 = 50% 0 = 17% bal1 1 = off 0 = on tog1 1 = off 0 = on ifb1 1 = off 0 = on lpc 1 = on 0 = off d1 d0 data data (pin 20) 12-bit transfer sens1 ball tgl fol h (high-z) sens2 item notes) when atsc is enabled, even if tg1 and tg2 are normal mode, tg1 and tg2 switch to gain up mode in conjunction with atsc. int is forcibly disabled regardless of the command when the tracking gain is increased. (including when the gain is increased b y atsc) when reset sens1 = fzc sens2 = high (hi-z) rdfct2 = 1 (reset) ifb1 to ifb6 = 0 (switch on) tog1 to tog4 = 0 (switch on) bal1 to bal4 = 1 (switch on) other data is "0".
? 39 CXA2542Q serial data truth table serial data focus control 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 0000 1000 0000 1001 0000 1010 0000 1011 0000 1100 0000 1101 0000 1110 0000 1111 0001 0000 0001 0001 0001 0010 0001 0011 0001 0100 0001 0101 0001 0110 0001 0111 0001 1000 0001 1001 0001 1010 0001 1011 0001 1100 0001 1101 0001 1110 0001 1111 $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0a $0b $0c $0d $0e $0f 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1a $1b $1c $1d $1e $1f 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 hex functions fs4 brak sld kick kick +1 kick +2 fig. 6 d2 tg1 tg2 tracking control fs2 fs1 notes) fs1 1: off 0: on fs2 1: on 0: off fs4 in the block diagram: 1:sw side 0:sw side notes) tg1 in the block diagram: 1:sw side 0:sw side tg2 1: off 0: on brake when d2 in fig. 6 is: 1: 1 0: 0 sled kick height d1 0 0 1 1 0 1 0 1 1 2 3 4 d0 relative value
? 40 CXA2542Q serial data tracking/sled mode 0010 0000 0010 0001 0010 0010 0010 0011 0010 0100 0010 0101 0010 0110 0010 0111 0010 1000 0010 1001 0010 1010 0010 1011 0010 1100 0010 1101 0010 1110 0010 1111 $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2a $2b $2c $2d $2e $2f 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 hex function tm6 tm5 tm4 tm3 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 tm2 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 tm1 notes) tm1/tm2 in the block diagram: 1:sw side 0:sw side tm3/tm4/tm5/tm6 1: on 0: off
? 41 CXA2542Q serial data $3xx 0011 0000 0000 0011 0000 0001 0011 0000 0010 0011 0000 0011 0011 0000 0100 0011 0000 0101 0011 0000 0110 0011 0000 0111 0011 0000 1000 0011 0000 1001 0011 0000 1010 0011 0000 1011 0011 0000 1100 0011 0000 1101 0011 0000 1110 0011 0000 1111 0011 0001 0000 0011 0001 0001 0011 0001 0010 0011 0001 0011 0011 0001 0100 0011 0001 0101 0011 0001 0110 0011 0001 0111 0011 0001 1000 0011 0001 1001 0011 0001 1010 0011 0001 1011 0011 0001 1100 0011 0001 1101 0011 0001 1110 0011 0001 1111 0011 0010 0000 0011 0010 0001 0011 0010 0010 0011 0010 0011 0011 0010 0100 0011 0010 0101 0011 0010 0110 0011 0010 0111 0011 0010 1000 0011 0010 1001 0011 0010 1010 0011 0010 1011 0011 0010 1100 0011 0010 1101 0011 0010 1110 0011 0010 1111 $300 $301 $302 $303 $304 $305 $306 $307 $308 $309 $30a $30b $30c $30d $30e $30f $310 $311 $312 $313 $314 $315 $316 $317 $318 $319 $31a $31b $31c $31d $31e $31f $320 $321 $322 $323 $324 $325 $326 $327 $328 $329 $32a $32b $32c $32d $32e $32f 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e d d d d d d d d d d d d d d d d hex bal sw 4 3 2 1 4 3 2 1 4 5 6 3 2 1 tog sw ifb sw int rdf ct2 atsc ldon lpcl lpc dfct tgfl
? 42 CXA2542Q serial data $3xx 0011 0011 0000 0011 0011 0001 0011 0011 0010 0011 0011 0011 0011 0011 0100 0011 0011 0101 0011 0011 0110 0011 0011 0111 0011 0011 1000 0011 0011 1001 0011 0011 1010 0011 0011 1011 0011 0011 1100 0011 0011 1101 0011 0011 1110 0011 0011 1111 0011 0100 0000 0011 0100 0001 0011 0100 0010 0011 0100 0011 0011 0100 0100 0011 0100 0101 0011 0100 0110 0011 0100 0111 0011 0100 1000 0011 0100 1001 0011 0100 1010 0011 0100 1011 0011 0100 1100 0011 0100 1101 0011 0100 1110 0011 0100 1111 0011 0101 0000 0011 0101 0001 0011 0101 0010 0011 0101 0011 0011 0101 0100 0011 0101 0101 0011 0101 0110 0011 0101 0111 0011 0101 1000 0011 0101 1001 0011 0101 1010 0011 0101 1011 0011 0101 1100 0011 0101 1101 0011 0101 1110 0011 0101 1111 $330 $331 $332 $333 $334 $335 $336 $337 $338 $339 $33a $33b $33c $33d $33e $33f $340 $341 $342 $343 $344 $345 $346 $347 $348 $349 $34a $34b $34c $34d $34e $34f $350 $351 $352 $353 $354 $355 $356 $357 $358 $359 $35a $35b $35c $35d $35e $35f 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 d d d d d d d d d d d d d d d d 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 hex bal sw 4 3 2 1 4 3 2 1 4 5 6 3 2 1 tog sw ifb sw int rdf ct2 atsc ldon lpcl lpc dfct tgfl
? 43 CXA2542Q serial data $3xx 0011 0110 0000 0011 0110 0001 0011 0110 0010 0011 0110 0011 0011 0110 0100 0011 0110 0101 0011 0110 0110 0011 0110 0111 0011 0110 1000 0011 0110 1001 0011 0110 1010 0011 0110 1011 0011 0110 1100 0011 0110 1101 0011 0110 1110 0011 0110 1111 0011 0111 0000 0011 0111 0001 0011 0111 0010 0011 0111 0011 0011 0111 0100 0011 0111 0101 0011 0111 0110 0011 0111 0111 0011 0111 1000 0011 0111 1001 0011 0111 1010 0011 0111 1011 0011 0111 1100 0011 0111 1101 0011 0111 1110 0011 0111 1111 0011 1000 0000 0011 1000 0001 0011 1000 0010 0011 1000 0011 0011 1000 0100 0011 1000 0101 0011 1000 0110 0011 1000 0111 0011 1000 1000 0011 1000 1001 0011 1000 1010 0011 1000 1011 0011 1000 1100 0011 1000 1101 0011 1000 1110 0011 1000 1111 $360 $361 $362 $363 $364 $365 $366 $367 $368 $369 $36a $36b $36c $36d $36e $36f $370 $371 $372 $373 $374 $375 $376 $377 $378 $379 $37a $37b $37c $37d $37e $37f $380 $381 $382 $383 $384 $385 $386 $387 $388 $389 $38a $38b $38c $38d $38e $38f 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 hex bal sw 4 3 2 1 4 3 2 1 4 5 6 3 2 1 tog sw ifb sw int rdf ct2 atsc ldon lpcl lpc dfct tgfl
? 44 CXA2542Q serial data $3xx 0011 1001 0000 0011 1001 0001 0011 1001 0010 0011 1001 0011 0011 1001 0100 0011 1001 0101 0011 1001 0110 0011 1001 0111 0011 1001 1000 0011 1001 1001 0011 1001 1010 0011 1001 1011 0011 1001 1100 0011 1001 1101 0011 1001 1110 0011 1001 1111 0011 1010 0000 0011 1010 0001 0011 1010 0010 0011 1010 0011 0011 1010 0100 0011 1010 0101 0011 1010 0110 0011 1010 0111 0011 1010 1000 0011 1010 1001 0011 1010 1010 0011 1010 1011 0011 1010 1100 0011 1010 1101 0011 1010 1110 0011 1010 1111 0011 1011 0000 0011 1011 0001 0011 1011 0010 0011 1011 0011 0011 1011 0100 0011 1011 0101 0011 1011 0110 0011 1011 0111 0011 1011 1000 0011 1011 1001 0011 1011 1010 0011 1011 1011 0011 1011 1100 0011 1011 1101 0011 1011 1110 0011 1011 1111 $390 $391 $392 $393 $394 $395 $396 $397 $398 $399 $39a $39b $39c $39d $39e $39f $3a0 $3a1 $3a2 $3a3 $3a4 $3a5 $3a6 $3a7 $3a8 $3a9 $3aa $3ab $3ac $3ad $3ae $3af $3b0 $3b1 $3b2 $3b3 $3b4 $3b5 $3b6 $3b7 $3b8 $3b9 $3ba $3bb $3bc $3bd $3be $3bf 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 hex bal sw 4 3 2 1 4 3 2 1 4 5 6 3 2 1 tog sw ifb sw int rdf ct2 atsc ldon lpcl lpc dfct tgfl
? 45 CXA2542Q serial data $3xx 0011 1100 0000 0011 1100 0001 0011 1100 0010 0011 1100 0011 0011 1100 0100 0011 1100 0101 0011 1100 0110 0011 1100 0111 0011 1100 1000 0011 1100 1001 0011 1100 1010 0011 1100 1011 0011 1100 1100 0011 1100 1101 0011 1100 1110 0011 1100 1111 0011 1101 0000 0011 1101 0001 0011 1101 0010 0011 1101 0011 0011 1101 0100 0011 1101 0101 0011 1101 0110 0011 1101 0111 0011 1101 1000 0011 1101 1001 0011 1101 1010 0011 1101 1011 0011 1101 1100 0011 1101 1101 0011 1101 1110 0011 1101 1111 0011 1110 0000 0011 1110 0001 0011 1110 0010 0011 1110 0011 0011 1110 0100 0011 1110 0101 0011 1110 0110 0011 1110 0111 0011 1110 1000 0011 1110 1001 0011 1110 1010 0011 1110 1011 0011 1110 1100 0011 1110 1101 0011 1110 1110 0011 1110 1111 $3c0 $3c1 $3c2 $3c3 $3c4 $3c5 $3c6 $3c7 $3c8 $3c9 $3ca $3cb $3cc $3cd $3ce $3cf $3d0 $3d1 $3d2 $3d3 $3d4 $3d5 $3d6 $3d7 $3d8 $3d9 $3da $3db $3dc $3dd $3de $3df $3e0 $3e1 $3e2 $3e3 $3e4 $3e5 $3e6 $3e7 $3e8 $3e9 $3ea $3eb $3ec $3ed $3ee $3ef 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 e e e e e e e e d d d d d d d d e e e e e e e e d d d d d d d d e e e e e e e e d d d d d d d d 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 hex bal sw 4 3 2 1 4 3 2 1 4 5 6 3 2 1 tog sw ifb sw int rdf ct2 atsc ldon lpcl lpc dfct tgfl
notes) 0 means off and 1 means on for tog sw and bal sw. these are not equal to the setting values of each bit for serial data. "? in the truth table indicates that the status does not change. tgfl in the block diagram: 1:sw side 0:sw side atsc e: enable/d: disable dfct e: enable/d: disable ? 46 CXA2542Q serial data $3xx 0011 1111 0000 0011 1111 0001 0011 1111 0010 0011 1111 0011 0011 1111 0100 0011 1111 0101 0011 1111 0110 0011 1111 0111 0011 1111 1000 0011 1111 1001 0011 1111 1010 0011 1111 1011 0011 1111 1100 0011 1111 1101 0011 1111 1110 0011 1111 1111 $3f0 $3f1 $3f2 $3f3 $3f4 $3f5 $3f6 $3f7 $3f8 $3f9 $3fa $3fb $3fc $3fd $3fe $3ff 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 e e e e e e e e d d d d d d d d 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 hex bal sw 4 3 2 1 4 3 2 1 4 5 6 3 2 1 tog sw ifb sw int rdf ct2 atsc ldon lpcl lpc dfct tgfl
? 47 CXA2542Q initial state (resetting state) item focus control tracking control tracking sled mode address d7 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 $00 $10 $20 d6 d5 d4 d3 d2 d1 d0 data hex item e-f balance tracking gain focus bias others address d11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 1 $300 $340 $380 $3d0 d10 d9 d8 d7 d6 d5 d4 0 0 0 0 d3 0 0 0 0 d2 0 0 0 0 d1 0 0 0 0 d0 data hex the above data means the following operation modes. focus control : focus off, focus search off, focus seach down tracking control : tg1-tg2 normal, brake disable, sled kick relative height value 1 tracking sled mode : tracking off, sled off e-f balance : bal1 to bal4 = 0 (switch on). dfct enable tracking gain : tog1 to tog4 = 0 (switch on), tgfl normal focus bias : ifb1 to ifb6 = 0 (switch on) others : int disable, dfct2 reset, atsc enable, ldon off, lpcl 17%, lpc off
? 48 CXA2542Q 2. sled amplifier the sled amplifier may oscillate when used by the buffer amplifier. use with a gain of approximately 20db. 3. focus/tracking internal phase compensation and reference design material notes on operation 1. focus ok circuit 1) refer to the "description of operation" for the time constant setting of the focus ok amplifier lpf and the mirror amplifier hpf. 2) the equivalent circuit for the output pin (fok) is shown in the diagram below. v c c 2 0 k 4 0 k 1 0 0 k v e e v e e r l f o k v c c 2 5 the fok and comparator output are as follows: output voltage high : v fokh near vcc output voltage low : v fokl vsat (npn) + v ee item sd measurement pin conditions typ. unit 1.2khz gain 1.2khz phase 1.2khz gain 1.2khz phase 2.7khz gain 2.7khz phase 08 08 25 25 25 ? 13 25 ? 13 6 c flb = 0.1 f c fgd = 0.1 f 21.5 63 13 ?25 26.5 ?30 db deg db deg db deg c tgu = 0.1 f 13 fcs trk 4. laser poser control the rf level is stabilized by attaching an offset to the apc v l and controlling the laser power in sync with the rf level fluctuations. the laser life is shortened by increasing the laser power when the less light is reflected from the disc. it is recommended that the typical laser power value is set lower to maintain the laser life. take care of the laser maximum ratings when using the laser power control circuit.
? 49 CXA2542Q package outline unit: mm s o n y c o d e e i a j c o d e j e d e c c o d e m p a c k a g e s t r u c t u r e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e w e i g h t e p o x y r e s i n s o l d e r / p a l l a d i u m p l a t i n g c o p p e r / 4 2 a l l o y 4 8 p i n q f p ( p l a s t i c ) 1 5 . 3 0 . 4 1 2 . 0 0 . 1 + 0 . 4 0 . 8 0 . 3 0 . 1 + 0 . 1 5 0 . 1 2 1 3 2 4 2 5 3 6 3 7 4 8 1 1 2 2 . 2 0 . 1 5 + 0 . 3 5 0 . 9 0 . 2 0 . 1 0 . 1 + 0 . 2 1 3 . 5 0 . 1 5 0 . 1 5 0 . 0 5 + 0 . 1 q f p - 4 8 p - l 0 4 * q f p 0 4 8 - p - 1 2 1 2 - b 0 . 7 g

▲Up To Search▲

Price & Availability of CXA2542Q

	To Download CXA2542Q Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .